There are a number of conventional processes for packaging integrated circuits. One approach that is commonly referred to as “flip chip” packaging generally contemplates forming solder bumps (or other suitable contacts) directly on the face of an integrated circuit die. In some situations, the contacts are formed directly on I/O pads formed on the die, whereas in other situations the contacts are redistributed. The die is then typically attached to a substrate such as a printed circuit board or package substrate such that the die contacts directly connect to corresponding contacts on the substrate.
In a number of packaging styles (including flip chip and other exposed die wafer level packaging styles) it is desirable to mark the back surface of the integrated circuit die/package. Depending upon the packaging contemplated, these markings may be made directly on a semiconductor material or on a back coating (e.g., polymeric protective coating). Typical marking may include designations such as an indication of the manufacturer or supplier of the devices, a part number, a “pin 1” designator, etc. To minimize costs, when possible, it is desirable to mark the devices at the wafer level.
In many applications the wafers are thinned (typically by backgrinding) in order to reduce the overall height of the resulting devices. As the desired thickness of semiconductor devices is reduced, it can become more difficult to perform the handling operations necessary to process (e.g. mark) the wafer after thinning. In the semiconductor industry, there are continuing efforts to increase device yield per wafer or lot and reduce the costs and time associated with semiconductor fabrication and packaging. The present invention seeks to provide more efficient approaches to marking the back surface of integrated circuits at the wafer level.